Senior ASIC RTL Engineer, Integration

Who you are

You have a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. With 8 years of experience in digital logic design principles and RTL design concepts, you are well-versed in languages such as Verilog or SystemVerilog. Your expertise extends to automation scripting languages like Perl, Python, and TCL, which you have used to enhance design processes. You possess a strong understanding of logic synthesis techniques aimed at optimizing area, performance, and power, as well as low-power design techniques. You have experience in integrating, designing, and automating flows of sub-systems and interconnects, including AXI 4/5, ACE-Lite, AHB, and APB.

You may also hold a Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science, and have 12 years of experience with digital logic design principles and basic RTL design concepts. Your background includes ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT. You are knowledgeable about high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture. Additionally, you have insights into memory compression, fabric, coherence, cache, or DRAM.

What you'll do

In this role, you will be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. Your contributions will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. You will interact closely with the architecture team to develop implementation strategies that meet quality, schedule, and PPA for the IP. Collaboration is key, as you will work closely with cross-functional teams including Verification, Design for Test, Physical Design, and Software teams to make informed design decisions and represent project status throughout the development process.

You will be responsible for integrating and automating flows of sub-systems and interconnects, ensuring that all components work seamlessly together. Your role will involve designing and optimizing logic for various components, focusing on performance and power efficiency. You will also engage in the verification process, ensuring that all designs meet the required specifications and standards. As you work on complex features in the IP/Subsystem, you will be expected to provide insights and recommendations based on your extensive experience in the field.

What we offer

At Google, you will be part of a culture that values innovation and collaboration. You will have the opportunity to work on cutting-edge technology that impacts millions of users worldwide. We encourage you to apply even if your experience doesn't match every requirement, as we value diverse perspectives and backgrounds. You will have access to professional development opportunities and the chance to work with some of the brightest minds in the industry, all while contributing to projects that matter.