SoC Physical Design Engineer, PnR

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product! In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process technology.

Description

• Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle. • Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals. • Timing, physical and electrical verification, and driving the signoff closure for the partitions. • Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution. • Drive optimization of PnR partitions, to achieve best Power/Performance/Area.

Minimum Qualifications

Minimum BS and 10+ years of relevant industry experience. Knowledge of partition level P&R implementation including floorplanning, clock and power distribution, timing closure, physical and electrical verification. Knowledge of physical design construction and analysis flows and methodology. Experience with industry standard tools, understanding their capabilities and underlying algorithms. Familiar with typical SOC issues such as multiple voltage and clock domains and mixed signal block integration.

Preferred Qualifications

MS in Electrical/Electronics/Computer Engineering or related field. Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ. Familiar with various process-related design issues including Design for Yield and Manufacturability and multi-vt strategies. From a CAD perspective, experience with floorplanning tools, P&R flows, global timing verification, and physical design verification flows. Ability to adhere to stringent schedule and die size requirements.

Eeo Content

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