Come and join Apple’s growing wireless silicon development team. Our Wireless SoC organization is responsible for all aspects of wireless silicon development, emphasizing highly energy-efficient design and new technologies that transform the user experience at the product level. This is driven by a world-class vertically integrated engineering team spanning RF/Analog, Systems/PHY/MAC, RTL design/integration, Emulation, Verification, DFT, Validation, and FW/SW engineering. We encourage you to apply if you enjoy a fast-paced and exciting environment, collaborating with people across different functional areas, and thrive during critical times.
Description
As a Timing Engineer, you will work in a team developing Wireless SoCs with custom hardware accelerators and multiple processor sub-systems. There will be the opportunity to work closely with SoC architects and IP developers to develop SoCs that meet power, performance, and area goals for Apple’s products. You will help improve the processes, methods, and tools for designing and implementing these large, complex SoCs. Collaboration with multi-disciplinary groups will be needed to make sure designs are delivered on time and with the highest quality by incorporating targeted checks at every stage of the design process. In this highly visible role, you will be at the center of the ASIC creation effort, interfacing with all disciplines, with a critical impact in getting leading-edge products launched to delight millions of customers.
Minimum Qualifications
Bachelors degree and 3+ years of relevant industry experience.
Timing constraint (SDC) creation at partition and chip level.
Logic synthesis execution (verilog RTL to netlist).
Preferred Qualifications
Strong knowledge of the entire ASIC design process, from RTL through synthesis, static timing analysis and place & route.
Expertise in STA tools and flow.
UPF usage for power and voltage islands.
Knowledge of timing corners, operating modes, process variation and signal integrity-related issues.
Skilled in scripting languages (TCL, PERL, Python), both standalone and within EDA tools.
Proficient in the closure of end-to-end logic equivalence (FV, LEC) with functional ECOs in the mix.
Familiarity with DFT approaches and constraints.
Proficient with RTL Verilog/VHDL.
Familiarity with digital top integration flows/methodology/checks.
Responsibilities
Full chip and block-level timing constraint creation, review and closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation).
Execute low power physical synthesis techniques, deploying knowledge of UPF and power intent verification.
Deploy and enhance methodology and flows related to timing constraint verification and timing closure.
Generation of consistent block and full chip timing constraints.
Support digital chip integration work and flows (e.g. CDC).
Collaborate with Chip Architecture, Design Verification, Physical Design, DFT, and power teams to achieve first time Silicon success.
Generally bridge between the RTL front end and place & route worlds.
Eeo Content
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
