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Home›Jobs›Google›Design for Testability Engineer Lead, Silicon
Google

About Google

Empowering the world through technology and information

🏢 Tech👥 100K+📅 Founded 1998📍 Mountain View, California, United States

Key Highlights

  • Over 100,000 employees globally
  • Headquartered in Mountain View, California
  • Parent company Alphabet Inc. valued at $1.5 trillion
  • Google Cloud Platform serves millions of customers

Google LLC, headquartered in Mountain View, California, is a global leader in internet-related services and products, including its flagship search engine, Google Search, and the Android operating system. With over 100,000 employees, Google also offers cloud computing services through Google Cloud P...

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Google offers competitive salaries, equity options, generous PTO policies, comprehensive health benefits, and a remote work policy that allows flexibi...

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Google is known for its engineering-first culture, emphasizing innovation and collaboration. The company fosters a unique environment that encourages ...

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Google

Design for Testability Engineer Lead, Silicon

Google • Bengaluru, Karnataka, India

Posted 4d agoLeadDesign for testability engineer📍 Bengaluru
Apply Now →

Skills & Technologies

DftDfdTessentGenusFcSimvisionAtpgJtagIjtagPython

Overview

Google is seeking a Design for Testability Engineer Lead to drive cross-functional design efforts and develop custom silicon solutions. You'll work with DFT methodologies and tools like Tessent and Python in Bengaluru.

Job Description

Who you are

You hold a Bachelor's degree in Computer Science, Electronics, or Electrical Engineering, or possess equivalent practical experience. With 8 years of experience in DFT/DFD flows and methodologies, you have a strong background in scan insertion, ATPG, gate level simulations, and silicon debug. Your expertise extends to low power designs, BIST, JTAG, and IJTAG tools and flows. You are proficient with IJTAG ICL, PDL terminology, ICL extraction, and ICL modeling using Siemens Tessent Tool. Additionally, you have experience with industry DFT, MBIST, and ATPG tools, and a solid understanding of high-performance design DFT techniques like SSN and HighBandwidth IJTAG. You are also skilled in scripting languages such as Perl or Python, which you use to automate and optimize DFT environments.

What you'll do

As the Design for Testability Engineer Lead at Google, you will be part of a team that pushes boundaries in developing custom silicon solutions that power the future of Google's direct-to-consumer products. You will collaborate with a team of DFT engineers across multiple voltage and power domains, driving cross-functional design efforts regarding memory repair methodology and system-level integration. You will own Gate-Level Simulation (GLS) verification and debug sign-off, ensuring total functional and timing coverage. Your responsibilities will include developing MBIST TbGen, pattern generation, and DFT simulation flows, as well as scripting to automate and optimize the DFT environment. Your contributions will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

What we offer

At Google, you will be part of a mission-driven team that combines the best of AI, software, and hardware to create radically helpful experiences. You will have the opportunity to work on innovative technologies and hardware that make computing faster, seamless, and more powerful. We encourage you to apply even if your experience doesn't match every requirement, as we value diverse perspectives and backgrounds. Join us in making people's lives better through technology.

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