Come and join Apple’s growing wireless silicon development team. Our wireless SoC organization is responsible for all aspects of wireless silicon development, emphasizing highly energy-efficient design and new technologies that transform the user experience at the product level. All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment, collaborate with people across different functional areas, and thrive during crisis times, we encourage you to apply.
Description
In this role you will work on a small team dedicated to implementing high performance, low power wireless SoCs from RTL to delivery of our final GDSII. There will be the opportunity to work closely with multi-disciplinary groups to meet power, performance, and area goals for Apple’s products. You will interact with RTL designers to understand design intent and clock structure, with CAD to understand and develop flows, with UPF and DFT teams to insert power and test structures, and with Physical design team to close and sign-off timing. Collaboration will be needed to make sure designs are delivered on time and with the highest quality by incorporating targeted checks at every stage of the design process. In this highly visible role, you will be at the center of the ASIC creation effort, interfacing with all disciplines, with a critical impact in getting leading-edge products launched to delight millions of customers.
Minimum Qualifications
BS and a minimum of 10 years relevant industry experience.
Knowledge of the ASIC design flow, synthesis, static timing analysis, RTL to Post Synthesis netlist.
Exposure to industry standard Timing, Logic Equivalence, Physical Design and Synthesis tools.
Proficient in scripting in TCL, Perl or Python.
Knowledge of basic SoC Architecture and HDL languages like Verilog / System Verilog to collaborate with our logic design team for timing fixes and functional ECOs.
Preferred Qualifications
Hands-on experience in timing/SDC constraints generation, analysis, and management.
Knowledge of timing corners, operating conditions, process variations, and signal integrity-related issues.
Knowledge of Place and Route steps including floor planning, CTS, Routing and timing ECOs.
Understanding of UPF and low-power design and implementation techniques.
Understanding of DFT methodologies including Scan and BIST.
Responsibilities
Generate chip or block level static timing constraints.
Synthesize design with UPF/DFT/BIST.
Close timing on critical blocks by working with design and PD teams.
Perform timing optimization and implement the design for functionality.
Generate and implement functional ECOs.
Run static timing analysis flows at chip/block level and provide guidelines to fix violations to other designers.
Participate in establishing/improving CAD and design flow methodologies.
Work with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating proper checks at every stage of the design process.
Eeo Content
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
