RFIC Layout Engineer

The Wireless SoC Radio Team designs state-of-art highly energy efficient CMOS radios, from RF to bits. To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and mixed-signal blocks from RF front-end amplifiers to data converters, including baseband filters, baseband and RF phase-locked loops, crystal oscillators, and bandgap references.

Description

As an RFIC Layout Engineer, you will be a key member of a RFIC team, researching, designing and bringing the next-generation of wireless technologies into high-volume production in advanced CMOS technology nodes.

Minimum Qualifications

BS and 3+ years of relevant industry experience. FinFet experience.

Preferred Qualifications

Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS. Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing. Solid understanding of RC delay, electromigration, and coupling. Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD and WPE. High level proficiency in interpretation of CALIBRE DRC, ERC, LVS in FinFet Technology. Knowledge of CADENCE layout tools. Excellent communication skills. Scripting skills in PERL or SKILL.

Responsibilities

Detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO. Block level layout through full verification flow including extraction, DRC, LVS, and DFM checking. Co-work with designers on block level floorplanning. Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling.

Eeo Content

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