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In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC using state of the art process technology.
Description
- Work with design teams to understand and debug constraints and facilitate logic changes to improve timing.
- Work with the Physical Design team, highlighting issues and best practices.
- Help create timing ECO’s for project tapeout.
- Create and maintain scripts and methodologies for analysis and runs.
- Create documentation and help with guidelines/specs.
- Deep analysis of timing paths to identify key issues.
- Implement timing infrastructure.
Minimum Qualifications
Minimum BS and 3+ years of relevant industry experience.
Experience with large design STA and Timing Closure.
Programming skills with Perl and TCL.
Preferred Qualifications
Hands-on experience in STA.
Familiar with important aspects of timing of large high-performance SoC designs in sub-micron technologies.
Proficient in STA and methodologies for timing closure and have a fundamental understanding of noise, crosstalk, and OCV effects, among others.
Familiar with circuit modeling, including SPICE models, and worst-case corner selection.
Familiar with ECO techniques and implementation.
Good communicator who can accurately describe issues and follow them through to completion.
Eeo Content
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
