Are you passionate about advancing the boundaries of RF analog circuit integration in advanced technology nodes for wireless transceivers? Do you thrive on innovation and improving RF layout methodologies? As an RFIC Layout Engineer, you will address intriguing daily layout challenges, collaborate with skilled RFIC design and layout teams, and continuously improve products to surpass previous iterations and enrich user experiences worldwide.
Description
You will lay out detailed custom blocks, including floorplanning, placement, routing, and verification for high-frequency RF circuits, verifying and refining layouts through simulation to meet design requirements. You will diagnose sophisticated verification (DRC/LVS) and PDK issues using Cadence and Calibre. Collaboration with engineering design and layout teams will be meaningful to understand design concepts, constraints, and opportunities for improvement. Upon identifying challenges, you will propose solutions to streamline layout tasks, collaborating with teams to specify and finalize methodologies.
Minimum Qualifications
BS with 3+ years of industry experience.
Deep knowledge of sub-micron CMOS technologies (16nm, 7nm, and beyond) and proficiency with FinFET structures, guard-rings, deep N-wells, and PN junctions are required.
Familiarity with sophisticated process effects such as LOD, WPE, and DFM is critical.
Understanding trade-offs involving matching, parasitic effects, high-frequency routing, isolation, coupling, shielding, RC delay, EM, IR, ESD, and latch-up is vital.
Preferred Qualifications
Experience in sophisticated DRC, ERC, LVS verification, and debugging.
Prior experience in crafting custom layouts at the chip, block, and device levels, particularly for RF high-frequency circuits such as LNAs, mixers, VCOs, and PLLs is a plus.
RF experience is helpful.
Responsibilities
Perform floorplanning, placement, routing, and verification for custom RF circuit blocks.
Verify and refine layouts through simulation to meet design requirements.
Diagnose sophisticated verification (DRC/LVS) and PDK issues using Cadence and Calibre.
Identify challenges and propose solutions to streamline layout tasks.
Collaborate with teams to specify and finalize layout methodologies.
Eeo Content
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