CPU Design Integration Engineer, Google Cloud

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, a related field, or equivalent practical experience.
• 4 years of experience with design from micro-architecture through implementation with Verilog/SystemVerilog, or VHSIC Hardware Description Language (VHDL).
• Experience in scripting.

Preferred qualifications:

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Excellent multitask and facilitation skills.
• Excellent problem-solving and communication skills.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

• Define and implement solutions for complex design, integration and verification problems using in-house and external technical solutions or tools. Ensure chip quality by implementing best practices and implementing quality control measures.
• Involve in project development and convergence with the highest quality, agreement with issues as they arise through design and implementation, or equivalent relevant experience.
• Connect between RTL design, physical design, DFT, external IPs and SoC while maintaining project priorities.
• Maintain project infrastructure and stability.