Senior Silicon Design Verification Engineer

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 8 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
  
• Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, caches, hierarchical memory subsystems, DDR/LPDDR).
• Experience in developing and maintaining verification testbenches, test cases, and test environments.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• 10 years of experience with creating and using verification components and environments in a standard verification methodology such as UVM and SV.
• Experience with low-power verification, debug, Gate-Level Simulation (GLS), and formal verification, with a track record of owning sub-system level verification and managing dependencies with key stakeholders.
• Experience in driving cross-functional teams for high quality tape-outs and leading design verification of complex IPs, successfully delivered to many SoCs.
• Proficiency in scripting languages (e.g., Python) for automation and analysis.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

• Plan the verification of digital design blocks at Sub System level by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Create and enhance constrained-random verification environments using SystemVerilog and UVM or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
• Identify and write all types of coverage measures for stimulus and corner-cases. And debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.
• Collaborate with architecture, design, SiVal, and Software (SW) teams to define the overall SoC verification strategy, serving as the primary point of contact for IP functional verification across cross-functional teams.