Senior ASIC DFT Engineer

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience.
• 5 years of experience with ATPG, low power designs, BIST, JTAG, IJTAG tools and flow.
• Experience with DFT EDA Tessent tools.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Proficient with IJTAG ICL, PDL terminology, ICL extraction, ICL modeling with Siemens Tessent Tool, Spyglass-DFT, DFT Scan constraints, and evaluating STA paths.
• Knowledge of high-performance design DFT techniques like SSN, high bandwidth IJTAG.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our Hardware team researches, designs, and develops new technologies and hardware to make our user's interaction with computing faster, more powerful, and seamless. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, our Hardware team is making people's lives better through technology.

• Work with a team of DFT Engineers, RTL and Physical Designer Engineers on subsystem level DFT SCAN, MBIST Architecture with multiple voltage, power domains.
• Work with junior members of the DFT team to deliver overall deliverables for two or more complex subsystems in a SoC.
• Write basic to complex scripts to automate the DFT flow.
• Develop tests that can be used for production in the ATE flow.
• Communicate and work with multi-disciplined and multi-site teams.