RTL Design Engineer, Google Cloud

Who you are

You hold a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or possess equivalent practical experience. With at least 4 years of experience in digital logic design principles and Register-Transfer Level (RTL) design concepts, you are well-versed in languages such as Verilog and System Verilog. Your background includes experience in logic design and debugging with Design Verification (DV), as well as familiarity with microarchitecture and specifications.

You have a strong understanding of logic synthesis techniques to optimize RTL code for performance and power, along with knowledge of low-power design techniques. Your experience extends to design sign-off and quality tools such as Lint, CDC, and VCLP. Additionally, you are proficient in a scripting language like Python or Perl, and possess knowledge of SoC architecture and assertion-based formal verification. You are familiar with areas such as PCIe, UCIe, DDR, AXI, and the ARM processors family, and have a keen interest in high-performance and low-power design techniques.

What you'll do

In this role, you will be part of a team that pushes boundaries by developing custom silicon solutions that power the future of Google's direct-to-consumer products. You will contribute to the innovation behind products loved by millions worldwide, shaping the next generation of hardware experiences that deliver unparalleled performance, efficiency, and integration. Your responsibilities will include using your ASIC design experience to develop complex ASIC System-on-Chip (SoC) intellectual property from proof-of-concept to production. This involves creating IP Level microarchitecture design documents, including interface protocols, block diagrams, transaction flows, and pipelines.

You will perform RTL development, coding, and debugging in Verilog and SystemVerilog, and conduct function and performance simulation debugging along with Lint, CDC, FV, and UPF checks. Engaging in synthesis, timing, and power closure, you will also be involved in ASIC silicon bring-up. Additionally, you will contribute to the verification test plan and coverage analysis of block and SoC-level designs, ensuring that the final product meets the highest standards of quality and performance.

What we offer

At Google, you will be part of a collaborative and innovative environment where your contributions will have a significant impact on the future of technology. We offer competitive compensation and benefits, along with opportunities for professional growth and development. You will work alongside some of the brightest minds in the industry, contributing to projects that are at the forefront of technology and shaping the future of hardware solutions. We encourage you to apply even if your experience doesn't match every requirement, as we value diverse perspectives and backgrounds.