Asic Jobs

SpaceX • Irvine, CA

SpaceX is seeking a SOC/ASIC Physical Design Engineer II to develop next-generation ASICs for deployment in space and ground infrastructures. You'll work on physical design tasks including synthesis, floorplanning, and verification. This role is based in Irvine, CA and requires expertise in ASIC design.

SpaceX • Sunnyvale, CA

SpaceX • Sunnyvale, CA

SpaceX • Irvine, CA

SpaceX • Redmond, WA

SpaceX • Irvine, CA

SpaceX • Sunnyvale, CA

SpaceX • Bastrop, TX

SpaceX is seeking a Physical Design Engineer II to develop next-generation ASICs for space and ground infrastructures. You'll perform physical implementation steps including synthesis and verification. This role is based in Bastrop, TX and requires expertise in ASIC design.

SpaceX • Redmond, WA

SpaceX • Sunnyvale, CA

SpaceX • Redmond, WA

SpaceX is seeking a Principal ASIC Design Engineer to develop cutting-edge FPGAs and ASICs for the Starlink project. You'll work on designing digital ASICs and evaluating architectural trade-offs to enhance connectivity solutions. This role requires expertise in ASIC and FPGA design.

Microsoft • United States, California, Santa Clara

Google • Tel Aviv, Israel, Haifa, Israel

Google is seeking a Senior Design Verification Engineer to develop verification components and environments for digital designs. You'll work with SystemVerilog and Specman/E to verify ASICs and FPGAs. This role requires 8 years of experience in verification methodologies and offers the opportunity to shape innovative hardware solutions.

Google • Haifa, Israel, Tel Aviv, Israel

Google is seeking a Senior Hardware Engineer to architect networking ASICs for Google Cloud. You'll develop Register-Transfer Level (RTL) designs and engage in cross-functional collaboration to optimize hardware/software interfaces. This role requires extensive experience in networking and ASIC development.

Google • Sunnyvale, CA, USA

Google is seeking a Senior ASIC Power Engineer to work on ML Accelerators in Sunnyvale. You'll focus on improving power efficiency for Tensor Processing Units (TPUs) and leverage your expertise in digital ASIC design and power management techniques. This role requires 5+ years of experience in logic design and low-power methodologies.

Amazon • Bengaluru, Karnataka, IND

Google • Tel Aviv, Israel, Haifa, Israel

Apple • Cupertino, California, United States

Apple • Austin, Texas, United States

Block • Bay Area, CA, United States of America

Google • Bengaluru, Karnataka, India

Google • New Taipei, Banqiao District, New Taipei City, Taiwan

Google • Bengaluru, Karnataka, India

Amazon • Austin, Texas, USA

Google • Tel Aviv, Israel, Haifa, Israel