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Google • Tel Aviv, Israel, Haifa, Israel
Google is seeking a Senior SoC and IP Design Engineer to develop custom silicon solutions for Google Cloud. You'll leverage your expertise in digital logic design, RTL design, and ASIC development. This role requires 8+ years of experience and knowledge of Verilog or SystemVerilog.
You have a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. With 8 years of experience in digital logic design principles and RTL design concepts, you are well-versed in languages such as Verilog or SystemVerilog. Your experience includes logic synthesis techniques to optimize RTL code, performance, and power, particularly with low-power design techniques. You are familiar with design sign-off and quality tools like Lint and CDC, and have a solid understanding of SOC architecture and logic design.
You may hold a Master's degree or PhD in Computer Science or a related technical field, which enhances your knowledge in areas such as Peripheral Component Interconnect Express (PCIe), Universal Chiplet Interconnect Express (UCIe), Double Data Rate (DDR), Advanced Extensible Interface (AXI), or the Advanced RISC Machines (ARM) processors family. Your expertise in high-performance and low-power design techniques, along with assertion-based formal verification, sets you apart. You possess excellent problem-solving and debugging skills, which are crucial for this role.
In this position, you will be part of a team that pushes boundaries by developing custom silicon solutions that power the future of Google's direct-to-consumer products. Your contributions will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. You will utilize your ASIC design experience to develop the ASIC SoC from Plan of Record (POR) to implementation, ensuring that all design specifications are met.
You will participate in function and performance simulation debugging, as well as Lint, Cyber Defense Center, Formal Verification, and Unified Power Format checks. Your role will also involve synthesis, timing and power closure, and ASIC silicon bring-up. You will engage in test plan and coverage analysis at both the block and SOC-level verification stages, providing valuable feedback on architecture.
At Google, you will be part of a collaborative and innovative environment where your work will have a significant impact on millions of users worldwide. We encourage you to apply even if your experience doesn't match every requirement, as we value diverse perspectives and backgrounds. You will have opportunities for professional growth and development, working alongside some of the brightest minds in the industry. Join us in shaping the future of technology and making a difference in the world.
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